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ELECTRONICS DESIGN ACRONYMS |
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Acronyms |
Domain |
Description |
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ASIC |
IC Designs |
Application Specific Integrated
Circuit |
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SOC |
IC Designs |
System on Chip |
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IP |
IC Designs |
Intellectual Property |
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P&R |
Tool |
Place & Route |
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HDL |
Design Data |
Hardware Descriptor Language |
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DEF |
P&R |
Design Exchange Format |
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LEF |
P&R |
Library Exchange Format |
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PDEF |
P&R |
Physical Design Exchange Format |
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DRC |
Layout Verification |
Design Rule Check |
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LVS |
Layout Verification |
Layout v/s Schematic |
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ERC |
Layout Verification |
Electric Rule Check |
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GDS |
Layout |
Graphic Design System
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CIF |
Layout |
Caltech Intermediate Format |
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VHDL |
Layout Verification |
Hardware Definition Language |
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EDIF |
Layout Verification |
Electronic Description Information
Format |
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AMS |
Layout Verification |
Analog Mixed Signal
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MPW |
Layout Verification |
Multi-Project Wafer
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SPF |
Parasitics |
Standard Parastic Format |
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DSPF |
Parasitics |
Detailed Standard Parastic Format |
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RSPF |
Parasitics |
Reduced Standard Parastic Format |
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SPEF |
Parasitics |
Standard Parastic Exchange Format |
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DFT |
IC Test |
Design For Test |
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JTAG |
IC Test |
Joint Test Action Group |
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ATPG |
IC Test |
Automatic Test-Pattern Generation |
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ATE |
IC Test |
Automatic Test Equipment |
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BIST |
IC Test |
Built-In Self Test |
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SDC |
Synthesis |
Synopsys Design Constraints |
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SAIF |
Power |
Switching Activity Interchange
Format |
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Stream |
Design Data |
GDSII Database import and export |
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Tape Out |
Foundry Services |
Mask Data ready for delivery to
foundry |
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